1. Field of the Invention
This invention relates generally to integrated circuits and, more particularly, to a method and apparatus for controlling simultaneous switching noise in an output bus configuration of very large scale integrated (VLSI) circuits.
2. Discussion of the Related Art
The fabrication of high performance VLSI devices permits the use of many functions on a single integrated circuit chip. The functional blocks on a single chip must be connected with a variety of other chips in order to receive data and communicate results within a computer system or other similar system. Communication between chips or functional blocks is faster when the data is transmitted in parallel over a large number of interconnections or bus. The electrical behavior of interconnections between functional blocks on a single chip is different than the behavior of interconnection between chips. The electrical resistance, capacitance, and inductance associated with packaging and interconnecting multiple chips affects the switching transitions of the signals sent between the chips. Therefore, the output drivers are used to compensate for these effects.
Output drivers generally drive a much larger capacitive load than an on-chip functional block would drive. To handle these large loads and meet required cycle times, output drivers have to drive high currents and have large di/dt's (corresponding to fast switching transition times). When a large number of these output drivers switch at the same time, the current demanded by the drivers can exceed the amount of current an integrated circuit package can supply to the on-chip power buses. When this happens, noise is generated on the chip and the buses "bounce" away from a card supply. The amount of noise depends on the speed of the drivers, the number of drivers switching, the design of the on-chip power buses and the electrical characteristics of the package. It is possible that the on-chip bus may be a volt or more away from the value of the same supply on the card. This much noise on a power supply can cause problems with signals being received on the same chip and can cause outputs that are not supposed to be switching to temporarily change states. Thus there exists a concern with simultaneous switching output drivers.
The stronger output signal coupled with a large number of output signals switching in parallel produces a noise problem on a single chip. Part of the noise problem is a result of a change in the current required by the input/output devices when many input/output devices are switched at once. The effects of the changes in current, also called current spikes, on the input/output devices vary depending on the placement of the drivers with respect to the power supply pins on the chip and the design of the power supply bussing. This is because current spikes must pass through the power supply bussing and its parasitic impedance. The placement of a switching input/output device with respect to the power supply pins changes the impedance which the current spikes encounter. Therefore, the voltage dropped across the impedance varies and this produces different effects on the input/output devices and other circuits near the input/output devices. In particular, when a current spike (i.e., noise) becomes large enough over a small enough impedance, an input/output device may (depending upon its position within a chip) switch its logical state unintentionally.
In an effort to reduce overall chip power consumption, the power supply bussing on a chip has the lowest impedance that is practical. A low impedance aggravates the noise problem because the current spike is not damped as it travels through the bussing so that it effects more circuits. Both a larger current spike and smaller impedances are likely when several input/output devices operate in parallel. Therefore, enhancing the signal speed and number of parallel input/output devices makes the chip communication more unreliable because the signals sent may not be correct due to the current noise (also referred to as Delta I noise) in the power supply.
Another part of the Delta I noise is that the current spike is an AC signal capacitively coupled to adjacent input/output devices through the parasitic capacitances between the input/output devices. The placement of the input/output devices determines the impedance through which the current spike passes. This impedance and size of the current spike determine the strength of the voltage signal capacitively coupled to the adjacent devices. If enough voltage is coupled to an adjacent input/output device through several input/output devices switching to one state simultaneously, and therefore having a cumulative effect, then the adjacent input/output device will switch logical state unintentionally. Again, switching logic signals are made more unreliable because of the Delta I noise.
As buses increase in size and transfer rates, the condition of simultaneous switching noise increases. The effect of this noise is a capping of a frequency and/or the increase in cost for packaging. At the same time, increasing complexity of processor architecture has resulted in the external bus to be the bottleneck. Some means of increasing the bus speed without increasing the simultaneous switching noise is needed.
Prior known solutions to this problem of simultaneous switching noise include the reducing of the speed of the transitions between the logic states of the input/output devices, however, the performance of the chip is undesirably limited by the Delta I noise. Another known technique is to filter out the current spikes. While filtering out the current spikes may be effective, the same may be prohibitively expensive because of packaging costs. Still another solution to the Delta I noise problem is to modify the parasitic elements on the power supply bussing for the chip itself. Typically, the later is done by using several input/output pins on the chip (rather than a single pin) for power supply connections. However, the number of input/output pins on a VLSI chip is generally limited. Therefore, the functionality of the chip is limited because the number of pins useful for logic signals is limited due to allocating extra pins for the power supply.